1. Field of the Invention
The present invention relates to a phase frequency detector for use in a phase locked loop (PLL) or a delay locked loop (DLL) and, more specifically, to a phase frequency detector capable of operating at a high frequency and having fast phase lock, low power consumption, and low noise characteristics.
2. Discussion of Related Art
A phase locked loop (hereinafter, referred to as PLL), which is a frequency feedback circuit that generates any frequency according to a predetermined clock signal, is used for a frequency synthesizer and a data processor, etc.
In general, the PLL includes a reference frequency generator, a voltage controlled oscillator (VCO), a frequency divider for dividing a frequency output from the VCO, a phase frequency detector (hereinafter, referred to as PFD) for receiving the reference frequency and the divided frequency to detect a phase, a charge pump for receiving a phase difference signal output from the PFD, and a loop filter for removing a high frequency component of a signal output from the charge pump. An output frequency of the VCO is controlled according to the voltage output through the loop filter.
The PFD receives the reference frequency and the divided frequency to output UP and DOWN signals. Here, the phase difference between two frequencies is represented by a difference of a pulse width of the UP and DOWN signals. When different frequencies are input, the frequency difference corresponds to a difference of the average pulse width of the UP and DOWN signals.
As shown in FIG. 1, the typical PFD includes flip-flops 1 and 2 for receiving a reference frequency clock CKref and a divided frequency clock CKout, respectively, to output the UP and DOWN signals; and a NAND gate 3 for logically combining the UP and DOWN signals to generate a reset signal for resetting the flip-flips 1 and 2.
Referring to FIG. 2, the UP signal becomes “1” at a rising edge of the reference frequency clock CKref and the DOWN signal becomes “1” at a rising edge of the divided frequency clock CKout. When both UP and DOWN signals become “1”, the flip-flops 1 and 2 are reset by the output of the NAND gate 3 so that both UP and DOWN signals become “0”. The UP signal which is the phase difference of the CKref and the CKout, is transferred to the charge pump so that the output frequency of the VCO is increased or decreased.
In the PFD used for the PLL, delay means is generally inserted into a reset path to prevent a dead zone such that certain duration pulses are simultaneously output through UP and DOWN signal output terminals when phases of two input clocks CKref and CKout are matched. The charge pump connected to the output stage of the PFD requires more than a certain number of duration pulses for an exact switching operation so that the extremely small delay means is not allowed in the reset path. Typically, a size of the delay means is typically determined such that the pulse duration time output through the UP and DOWN signal output terminals is 300 ps or more.
As the pulse duration output through the UP and DOWN signal output terminals become longer, Δ in FIG. 3 becomes larger. In this case, when the UP and DOWN signals are output in a reversed direction rather than the fixed direction, a time required for phase lock becomes longer. In addition, as the frequencies of the input clocks CKref and CKout become higher, a ratio of the pulse width for preventing the dead zone to the compared clock period becomes larger. Therefore, Δ becomes larger and the operation speed of the PFD reaches a limitation. When Δ is more than π, the phase lock is not guaranteed. [Ref. Mansuri M. etc. “Fast frequency acquisition phase-frequency detectors for Gsamples/s phase-locked loops”, Solid-State Circuits, IEEE Journal of Vol. 37, pp 1331–1334, 2002. 10.].
Mansuri M. etc. proposed a phase frequency detector arranged as in FIG. 4 to improve the problems. FIG. 5 is a waveform showing the operation characteristics of the phase frequency detector shown in FIG. 4, which shows that the time for locking phase becomes shorter.
When a phase error is close to 2π, pulses Pref and Pout delayed by an inverter remain high during a predetermined time after a falling edge of the reset signal RST so that right UP and DOWN signals are output. When the predetermined time is t1, an ON current of transistors N1, N2, N3 or N4, N5, N6 connected in series should be sufficient to change a state of the latch to output the UP and DOWN signals as high states during t1 time. For the operation of the fast phase lock, the state of the latch should be changed even when t1 is extremely short. Therefore, channel widths of the transistors N1, N2, N3 or N4, N5, N6 should be large so that it is difficult to reduce power consumption.